Field of the Invention
The invention lies in the integrated technology field. More specifically, the invention relates to an integrated ferroelectric or DRAM semiconductor memory configuration, in which a selection transistor and a storage capacitor which can be addressed by the selection transistor are provided on a substrate wafer per memory cell.
A DRAM semiconductor memory configuration of this type is disclosed in U.S. Pat. Nos. 4,959,709 and 4,978,635, and in the corresponding German patent application DE 38 40 559 A1.
The magnitude of the switchable polarization or the charge that can be stored on the capacitor plates is of crucial importance for the functionality and also the reliability of ferroelectric memories (FeRAMS) and DRAMs having a high dielectric constant (∈). The voltage on the bit line (BL) which is caused by the polarization or charge during reading must not fall below a minimum value specified for the product. In the simplest case, the BL signal can be increased by enlarging the capacitor area. However, this is accompanied by an enlargement of the chip area.
Attempts have already been made to achieve the BL signal through a suitable choice of the dielectric or ferroelectric (high dielectric constant ∈), reduction of the thickness of the dielectric, and also by means of design optimizations (low BL capacitance). However, technological limits are imposed on these methods, and the conventional pursuits therefore, lead to the enlargement of the capacitor area at the expense of the packing density.
The semiconductor memory device disclosed in the above-noted prior art disclosures (U.S. Pat. Nos. 4,959,709, 4,978,635, and DE 38 40 559 A1) above has a storage capacitor formed as a trench capacitor in a trench formed from the rear side of a silicon substrate.
It is accordingly an object of the invention to provide an integrated ferroelectric or DRAM semiconductor memory configuration, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which makes available an enlarged capacitor area for each memory cell, and thus enables an increase in the switchable polarization or the charge that can be stored on the capacitor plates in order to increase the BL signal without reducing the packing density of the memory cells.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory configuration, such as a ferroelectric or a DRAM memory configuration, comprising:
a substrate having a front side and a rear side;
a plurality of memory cells each having a selection transistor and a storage capacitor connected to and addressible by the selection transistor;
the storage capacitors of respectively successive memory cells being formed alternately on the front side and the rear side of the substrate; and
plugs formed on the rear side of the substrate, the plugs electrically connecting an electrode region of a respective the selection transistor with a capacitor plate, facing toward the selection transistor, of the storage capacitor disposed on the rear side of the substrate.
In accordance with an added feature of the invention, the rear side of the substrate is formed with a depression and an insulating layer formed in the depression, and wherein the storage capacitors formed on the rear side are disposed in the insulating layer and the insulating layer protects the storage capacitors from an influence of subsequent processes.
In accordance with an additional feature of the invention, the selection transistors of the memory cells are CMOS transistors formed from the front side of the substrate wafer.
In accordance with a concomitant feature of the invention, the storage capacitors formed on the front side of the substrate extend in a lateral direction to partly overlap a selection transistor of the adjacent the memory cell.
In other words, every other storage capacitor is formed on the rear side of the wafer. As a result, the storage capacitors can occupy a larger capacitance-forming area, which has an effective consequence in terms of increasing the corresponding read signal. Moreover, plugs are formed on the rear side of the substrate wafer, which plugs electrically connect an electrode region of the associated selection transistor to the capacitor plate, facing toward the selection transistor, of the storage capacitor situated on the rear side of the substrate wafer.
By incorporating the rear side of the wafer, it is possible to achieve more effective utilization of the chip area. Consequently, with no loss of chip area, the capacitor area can be made larger than in conventional technologies in which only the front side of the wafer is utilized. By virtue of the increased BL signal, the cell size can be miniaturized still further and the reliability of the memory product can be increased.
Applying semiconductor circuits to the front and rear sides of a silicon wafer is known, as described in German published patent application DE 39 14 055 A1. By means of that known two-sided process of the silicon wafer, however, a functionally continuous circuit is not applied from both sides of the silicon wafer, but rather a multiplicity of circuits which are functionally isolated from one another. This is done in the prior art in order to increase the number of semiconductor functions that can be realized per unit area.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.